Power-supply current monitoring for testing of CMOS logic circuits monitors the current passing through the power supply VDD or ground GND terminals during the application of an input stimulus or while the circuit is in a quiescent condition.
Many of the existing current monitors, however, fail to provide reliable monitoring due to fluctuation in process, temperature, and voltage supply.
FIG. 1 illustrates a voltage regulator arrangement connected to a current monitor 20. The voltage regulator includes a closed loop, wherein amplifier 12 couples to drive main FET 16. Main FET 16 is connected to a resistor divider represented by resistors R2, R8, R7, and R3. The connection from the voltage divider is fed back to the inverted input of amplifier, wherein the reference or bandgap voltage Vref is fed into the non-inverting input of the amplifier. The following equation applies when deriving the value of the generated voltage VCC:VCC=Vref(1+(R8+R2)/(R7+R3))
The current monitor 20 includes a sense FET 14, having a control node, a source node and a drain node, a resistor R6, a transistor Q1, a diode D1, and a resistor R4. The control node of sense FET 14 connects to amplifier 14. In operation, the current that goes through the sense FET 14 is divided down by n since the size of sense FET 14 is 1/n times the size of the main FET 16, where n is some integer value (i.e. 2, 3, 4, etc.). This same current flows across resistor R6 and generates a voltage that is equivalent to the base emitter voltage of transistor Q1. Once the voltage across resistor R6 is greater than the quiescent threshold voltage (˜0.7V) of transistor Q1, transistor Q1 turns on. As a result, node P is pulled down and, thereby, the main FET 16 is turned off. Accordingly, excess current is prevented from flowing through main FET 16 after the threshold is reached.
Problems arise when the variations of process, temperature, voltage of the main FET 16, sense FET 14, and resistor R6 cause the voltages to vary and, thereby, creating voltage mismatches within the circuit. If the drain-to-source voltage VDS across main FET 16 and sense FET 14 do not match, the basic equation for the generating voltage VCC will be defeated.
FIG. 2 shows another known current monitor 60 connected to sense the current of voltage regulator 80. The voltage regulator 80 includes amplifier 52 coupled to the gate of the main FET 54. The drain of the main FET 54 connects to resistors R10 and R12 which form a voltage divider to be fed back to the inverting input of amplifier 10. In operation, the voltage regulator incorporates a closed loop using amplifier 52 which drives main FET 54. The main FET 54 is connected to a voltage divider represented by resistors, R10 and R12. The connection from the voltage divider is fed back to the inverted input of amplifier 52, where the reference or bandgap voltage Vref is fed into the non-inverting input of amplifier 52. The following equation applies when deriving the value of VCC:VCC=Vref(1+(R10)/(R12))
Current monitor 60 includes a sense FET 62 coupled to an amplifier 64 that includes a feedback loop. Since the feedback loop exists, the voltage at node B1 is controlled. It is necessary to make certain that the voltage at node A1 equals the voltage at node B1. The current Ilim/n represents the feedback current ifdb that flows through resistor R16. The voltage at node C1 is represented in the following equation:Vnode C1=Vsupply−R16(Ilim/n).Amplifier 64 controls transistor 66 such that the current through resistors, R16 and R18, changes to make sure that the voltage at nodes A1 and B1 remain the same.
In operation, if the voltage at node B1 is greater than the voltage at node A1 by for example 100 mV, the gate voltage of transistor 66 will rise since the gate to source voltage will increase. Initially transistor 66 is in the saturation region, once the gate to source voltage Vgs increases, the feedback current ifdb will decrease to try to match and make the voltage at node A1 equivalent to that of node B1, such that the voltage at node B1 will decrease to equalize to that of node A1.
When the voltage at node A1 is greater than that of node B1, however, the current that flows through transistor 66 will decrease and the feedback current ifdb will increase to try to match and force transistor 66 into the saturation region. Thereby, the voltage at node B1 will increase to that of node A1.
Problems arise when the transistors process varies, thereby the voltage and current values will differ. In addition, when the temperature and supply voltage changes, this type of current monitor fails to provide a reliable determination due to drain-to-source voltage mismatch of main FET 54 and sense FET 62.
Thus, a need exists for a current monitor having a high performance, simple, and cost effective design that is independent of process, temperature and voltage.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.